The present invention relates to the fabrication of Si-based devices such as micro-electromechanical systems (MEMS) having high aspect ratio openings formed in a substrate thereof. More particularly, the present invention relates to a method of fabricating at least one deep opening having substantially smooth and nearly vertical sidewalls in a Si-containing substrate. The openings formed in the present invention, which can be useful for fabricating MEMS, have a depth, as measured from a top surface of the Si-containing substrate to the etched bottom wall, of about 50 microns, xcexcm, or greater and an aspect (depth to width) ratio of about 10:1 or greater.
In the field of semiconductor and magnetic device manufacturing, lithography and etching are generally employed to provide an opening into a substrate. Typically, the substrate is patterned by steps which include: applying a resist to a surface of the substrate, exposing the resist to a pattern of radiation, developing the patterned resist using a suitable resist developer to expose a portion of the underlying substrate, and etching the exposed portion of the substrate by a dry etching process such as reactive-ion etching (RIE) where chlorine-based or fluorine-based chemistries are employed.
Although conventional lithography and etching can be used to form such a feature in most types of semiconductor and magnetic devices, problems arise when deep Si features are needed for MEMS type devices as well as other Si-based devices. These problems include: a low etching rate, and/or lateral etching.
For example, when conventional RIE techniques utilizing chlorine-based chemistries are employed to form deep Si features, the etch rates are extremely slow (on the order of 500 xc3x85/min or less). The creation of a very deep opening of 100 xcexcm or more therefore requires unreasonably long cycle times. Faster etch rates can be achieved using fluorine-based chemistries, however, the resultant etch is too isotropic for forming deep Si features. That is, fluorine-based chemistries cause lateral etching to occur, in addition to the desired vertical etching of the deep Si features.
Enhanced RIE systems such as an Inductively Coupled Plasma (ICP) system can produce the higher etching rates required to satisfy cycle time requirements, but ICP systems usually do not etch anisotropically using fluorine-based chemistries or they do not demonstrate adequate selectively to the masking material using chlorine-based chemistries. A solution to the above problems (i.e., fast etching rates, non-lateral etching, and selectively to the mask) is to use a process where a series of separate etching and deposition steps are employed. In such a process, a portion of the Si-containing substrate to include the feature is anisotropically etched and then the gas phase plasma chemistry is changed and a passivation layer is formed on the etched sidewalls. This sequence of etching and deposition is cycled until the desired deep Si features are formed.
In this prior art process, dimensional control is maintained by the deposited sidewall passivation layer, but the sidewall features will consist of a series of steps (or staircases) formed as the process moves from an etch phase to a deposition phase if the chemistry is not under precise control. Moreover, special equipment modifications are needed to execute this process which adds extra cost to the overall device fabrication process.
A method is thus needed which is capable of forming deep openings in a Si-containing substrate wherein a fast etch rate is obtained without causing unwanted lateral etching. A method is also needed in which a fast etch rate and non-lateral etching can be achieved without the requirement of using separate etching and deposition processing steps.
The present invention provides a cost efficient and simple method for forming deep openings (on the order of about 50 xcexcm or greater) in a surface of a Si-containing substrate. The inventive method is capable of forming deep openings that have a high aspect ratio (on the order of about 10:1 or greater). Moreover, the method of the present invention is capable of providing the above-mentioned deep openings while maintaining precise dimensional control. The inventive method also provides deep openings having nearly vertical sidewalls that are substantially smooth and residue free. The term xe2x80x9copeningxe2x80x9d is used herein to denote a breached region or area that can be formed into a Si-containing substrate. The breached region or area is typically three-dimensional. Illustrative examples of such openings include, but are not limited to: apertures, holes, tunnels, trenches, moats, passageways, vias, and gaps.
The method of the present invention is capable of forming deep openings in a Si-containing substrate at extremely fast etching rates ( greater than 500xc3x85/min), without causing unwanted lateral etching Moreover, the deep openings are formed in the present invention without the need for using the sequential etching and deposition steps typically employed in the prior art.
Specifically, the method of the present invention includes first forming a thin Ni hardmask on a surface of a Si-containing substrate. The Ni hardmask is patterned using conventional photolithography and wet etching so as to expose at least one portion of the underlying Si-containing substrate. The at least one exposed portion of the Si-containing substrate, not containing the patterned hardmask, is then etched in a plasma that includes free radicals generated from a gaseous mixture of chlorine (Cl2), sulfur hexafluoride (SF6) and oxygen (O2). The interaction of the gas species in the plasma yields a rapid silicon etch rate that is highly selective to the Ni hardmask. The etch rate ratio of Si to Ni using the inventive method is greater than 250:1.
Without wishing to be bound by any theory, it is believed that the addition of SF6 to Cl2 increases the Si etch rate. Moreover, it is believed that, during the course of the inventive etching step, chloro-fluoro compounds, such as ClF and ClF3, form which control the amount of free atomic fluorine in the plasma and therefore control lateral etching. Oxygen is present in the inventive etching step to produce a nonvolatile nickel oxide layer on the Ni hardmask, providing high selectivity. During the course of the inventive etching step, a passivation layer is simultaneously deposited on the vertical sidewalls of the etched Si-containing substrate. This deposition of the passivation layer occurs in-situ and does not involve a separate deposition processing step or tool. The passivation layer is believed to be a compound of nickel oxide which inhibits lateral etching and gives the inventive method its anisotropic qualities.
The passivation layer that remains on the sidewalls after etching can be removed by a conventional wet chemical etching process providing at least one opening in the Si-containing substrate that has substantially smooth and nearly vertical sidewalls as well as a clean and smooth bottom wall.
In broad terms, the method of the present invention comprises the steps of:
forming a patterned Ni hardmask on a surface of a Si-containing substrate, said patterned Ni hardmask including at least one hole that exposes a portion of the Si-containing substrate;
etching the exposed portion of the Si-containing substrate in the presence of a plasma that includes free radicals generated from a gaseous mixture of Cl2, SF6 and O2 to provide at least one opening in the Si-containing substrate, said at least one opening
having sidewalls that extend to a common bottom wall, wherein during the etching a passivation layer forms at least on the sidewalls of said at least one opening; and
removing the passivation layer from the sidewalls to provide said at least one opening with substantially smooth and nearly vertical sidewalls.
The term xe2x80x98substantially smoothxe2x80x99 is used herein to denote sidewalls that contain little or no divot regions therein, while the term xe2x80x98nearly verticalxe2x80x99 denotes sidewalls that are approximately perpendicular to an upper horizontal surface of the Si-containing substrate. Some negligible tapering may occur using the inventive etching step of the present invention.